/GCC 4

3.17.5 AVR Options

These options are defined for AVR implementations:

Specify Atmel AVR instruction set architectures (ISA) or MCU type.

The default for this option is avr2.

GCC supports the following AVR devices and ISAs:

“Classic” devices with up to 8 KiB of program memory. mcu = attiny22, attiny26, at90c8534, at90s2313, at90s2323, at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515, at90s8535.
“Classic” devices with up to 8 KiB of program memory and with the MOVW instruction. mcu = ata5272, ata6289, attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny25, attiny261, attiny261a, attiny43u, attiny4313, attiny44, attiny44a, attiny45, attiny461, attiny461a, attiny48, attiny84, attiny84a, attiny85, attiny861, attiny861a, attiny87, attiny88, at86rf401.
“Classic” devices with 16 KiB up to 64 KiB of program memory. mcu = at43usb355, at76c711.
“Classic” devices with 128 KiB of program memory. mcu = atmega103, at43usb320.
“Classic” devices with 16 KiB up to 64 KiB of program memory and with the MOVW instruction. mcu = ata5505, atmega16u2, atmega32u2, atmega8u2, attiny1634, attiny167, at90usb162, at90usb82.
“Enhanced” devices with up to 8 KiB of program memory. mcu = ata6285, ata6286, atmega48, atmega48a, atmega48p, atmega48pa, atmega8, atmega8a, atmega8hva, atmega8515, atmega8535, atmega88, atmega88a, atmega88p, atmega88pa, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81.
“Enhanced” devices with 16 KiB up to 64 KiB of program memory. mcu = ata5790, ata5790n, ata5795, atmega16, atmega16a, atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, atmega16m1, atmega16u4, atmega161, atmega162, atmega163, atmega164a, atmega164p, atmega164pa, atmega165, atmega165a, atmega165p, atmega165pa, atmega168, atmega168a, atmega168p, atmega168pa, atmega169, atmega169a, atmega169p, atmega169pa, atmega26hvg, atmega32, atmega32a, atmega32c1, atmega32hvb, atmega32hvbrevb, atmega32m1, atmega32u4, atmega32u6, atmega323, atmega324a, atmega324p, atmega324pa, atmega325, atmega325a, atmega325p, atmega3250, atmega3250a, atmega3250p, atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, atmega3290pa, atmega406, atmega48hvf, atmega64, atmega64a, atmega64c1, atmega64hve, atmega64m1, atmega64rfa2, atmega64rfr2, atmega640, atmega644, atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, at90can32, at90can64, at90pwm161, at90pwm216, at90pwm316, at90scr100, at90usb646, at90usb647, at94k, m3000.
“Enhanced” devices with 128 KiB of program memory. mcu = atmega128, atmega128a, atmega128rfa1, atmega1280, atmega1281, atmega1284, atmega1284p, at90can128, at90usb1286, at90usb1287.
“Enhanced” devices with 3-byte PC, i.e. with more than 128 KiB of program memory. mcu = atmega2560, atmega2561.
“XMEGA” devices with more than 8 KiB and up to 64 KiB of program memory. mcu = atmxt112sl, atmxt224, atmxt224e, atmxt336s, atxmega16a4, atxmega16a4u, atxmega16c4, atxmega16d4, atxmega32a4, atxmega32a4u, atxmega32c4, atxmega32d4, atxmega32e5, atxmega32x1.
“XMEGA” devices with more than 64 KiB and up to 128 KiB of program memory. mcu = atxmega64a3, atxmega64a3u, atxmega64a4u, atxmega64b1, atxmega64b3, atxmega64c3, atxmega64d3, atxmega64d4.
“XMEGA” devices with more than 64 KiB and up to 128 KiB of program memory and more than 64 KiB of RAM. mcu = atxmega64a1, atxmega64a1u.
“XMEGA” devices with more than 128 KiB of program memory. mcu = atmxt540s, atmxt540sreva, atxmega128a3, atxmega128a3u, atxmega128b1, atxmega128b3, atxmega128c3, atxmega128d3, atxmega128d4, atxmega192a3, atxmega192a3u, atxmega192c3, atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, atxmega256a3u, atxmega256c3, atxmega256d3, atxmega384c3, atxmega384d3.
“XMEGA” devices with more than 128 KiB of program memory and more than 64 KiB of RAM. mcu = atxmega128a1, atxmega128a1u, atxmega128a4u.
This ISA is implemented by the minimal AVR core and supported for assembler only. mcu = attiny11, attiny12, attiny15, attiny28, at90s1200.
Accumulate outgoing function arguments and acquire/release the needed stack space for outgoing function arguments once in function prologue/epilogue. Without this option, outgoing arguments are pushed before calling a function and popped afterwards.

Popping the arguments after the function call can be expensive on AVR so that accumulating the stack space might lead to smaller executables because arguments need not to be removed from the stack after such a function call.

This option can lead to reduced code size for functions that perform several calls to functions that get their arguments on the stack like calls to printf-like functions.

Set the branch costs for conditional branch instructions to cost. Reasonable values for cost are small, non-negative integers. The default branch cost is 0.
Functions prologues/epilogues are expanded as calls to appropriate subroutines. Code size is smaller.
Assume int to be 8-bit integer. This affects the sizes of all types: a char is 1 byte, an int is 1 byte, a long is 2 bytes, and long long is 4 bytes. Please note that this option does not conform to the C standards, but it results in smaller code size.
Generated code is not compatible with hardware interrupts. Code size is smaller.
Try to replace CALL resp. JMP instruction by the shorter RCALL resp. RJMP instruction if applicable. Setting -mrelax just adds the --relax option to the linker command line when the linker is called.

Jump relaxing is performed by the linker because jump offsets are not known before code is located. Therefore, the assembler code generated by the compiler is the same, but the instructions in the executable may differ from instructions in the assembler code.

Relaxing must be turned on if linker stubs are needed, see the section on EIND and linker stubs below.

Treat the stack pointer register as an 8-bit register, i.e. assume the high byte of the stack pointer is zero. In general, you don't need to set this option by hand.

This option is used internally by the compiler to select and build multilibs for architectures avr2 and avr25. These architectures mix devices with and without SPH. For any setting other than -mmcu=avr2 or -mmcu=avr25 the compiler driver will add or remove this option from the compiler proper's command line, because the compiler then knows if the device or architecture has an 8-bit stack pointer and thus no SPH register or not.

Use address register X in a way proposed by the hardware. This means that X is only used in indirect, post-increment or pre-decrement addressing.

Without this option, the X register may be used in the same way as Y or Z which then is emulated by additional instructions. For example, loading a value with X+const addressing with a small non-negative const < 64 to a register Rn is performed as

adiw r26, const   ; X += const
ld   Rn, X        ; Rn = *X
sbiw r26, const   ; X -= const
Only change the lower 8 bits of the stack pointer.
Warn about conversions between address spaces in the case where the resulting address space is not contained in the incoming address space. EIND and Devices with more than 128 Ki Bytes of Flash

Pointers in the implementation are 16 bits wide. The address of a function or label is represented as word address so that indirect jumps and calls can target any code address in the range of 64 Ki words.

In order to facilitate indirect jump on devices with more than 128 Ki bytes of program memory space, there is a special function register called EIND that serves as most significant part of the target address when EICALL or EIJMP instructions are used.

Indirect jumps and calls on these devices are handled as follows by the compiler and are subject to some limitations:

  • The compiler never sets EIND.
  • The compiler uses EIND implicitely in EICALL/EIJMP instructions or might read EIND directly in order to emulate an indirect call/jump by means of a RET instruction.
  • The compiler assumes that EIND never changes during the startup code or during the application. In particular, EIND is not saved/restored in function or interrupt service routine prologue/epilogue.
  • For indirect calls to functions and computed goto, the linker generates stubs. Stubs are jump pads sometimes also called trampolines. Thus, the indirect call/jump jumps to such a stub. The stub contains a direct jump to the desired address.
  • Linker relaxation must be turned on so that the linker will generate the stubs correctly an all situaltion. See the compiler option -mrelax and the linler option --relax. There are corner cases where the linker is supposed to generate stubs but aborts without relaxation and without a helpful error message.
  • The default linker script is arranged for code with EIND = 0. If code is supposed to work for a setup with EIND != 0, a custom linker script has to be used in order to place the sections whose name start with .trampolines into the segment where EIND points to.
  • The startup code from libgcc never sets EIND. Notice that startup code is a blend of code from libgcc and AVR-LibC. For the impact of AVR-LibC on EIND, see the AVR-LibC user manual.
  • It is legitimate for user-specific startup code to set up EIND early, for example by means of initialization code located in section .init3. Such code runs prior to general startup code that initializes RAM and calls constructors, but after the bit of startup code from AVR-LibC that sets EIND to the segment where the vector table is located.
    #include <avr/io.h>
    static void
    init3_set_eind (void)
      __asm volatile ("ldi r24,pm_hh8(__trampolines_start)\n\t"
                      "out %i0,r24" :: "n" (&EIND) : "r24","memory");

    The __trampolines_start symbol is defined in the linker script.

  • Stubs are generated automatically by the linker if the following two conditions are met:
    • The address of a label is taken by means of the gs modifier (short for generate stubs) like so:
      LDI r24, lo8(gs(func))
      LDI r25, hi8(gs(func))
    • The final location of that label is in a code segment outside the segment where the stubs are located.
  • The compiler emits such gs modifiers for code labels in the following situations:
    • Taking address of a function or code label.
    • Computed goto.
    • If prologue-save function is used, see -mcall-prologues command-line option.
    • Switch/case dispatch tables. If you do not want such dispatch tables you can specify the -fno-jump-tables command-line option.
    • C and C++ constructors/destructors called during startup/shutdown.
    • If the tools hit a gs() modifier explained above.
  • Jumping to non-symbolic addresses like so is not supported:
    int main (void)
        /* Call function at word address 0x2 */
        return ((int(*)(void)) 0x2)();

    Instead, a stub has to be set up, i.e. the function has to be called through a symbol (func_4 in the example):

    int main (void)
        extern int func_4 (void);
        /* Call function at byte address 0x4 */
        return func_4();

    and the application be linked with -Wl,--defsym,func_4=0x4. Alternatively, func_4 can be defined in the linker script. Handling of the RAMPD, RAMPX, RAMPY and RAMPZ Special Function Registers

Some AVR devices support memories larger than the 64 KiB range that can be accessed with 16-bit pointers. To access memory locations outside this 64 KiB range, the contentent of a RAMP register is used as high part of the address: The X, Y, Z address register is concatenated with the RAMPX, RAMPY, RAMPZ special function register, respectively, to get a wide address. Similarly, RAMPD is used together with direct addressing.

  • The startup code initializes the RAMP special function registers with zero.
  • If a named address space other than generic or __flash is used, then RAMPZ is set as needed before the operation.
  • If the device supports RAM larger than 64 KiB and the compiler needs to change RAMPZ to accomplish an operation, RAMPZ is reset to zero after the operation.
  • If the device comes with a specific RAMP register, the ISR prologue/epilogue saves/restores that SFR and initializes it with zero in case the ISR code might (implicitly) use it.
  • RAM larger than 64 KiB is not supported by GCC for AVR targets. If you use inline assembler to read from locations outside the 16-bit address range and change one of the RAMP registers, you must reset it to zero after the access. AVR Built-in Macros

GCC defines several built-in macros so that the user code can test for the presence or absence of features. Almost any of the following built-in macros are deduced from device capabilities and thus triggered by the -mmcu= command-line option.

For even more AVR-specific built-in macros see AVR Named Address Spaces and AVR Built-in Functions.

Build-in macro that resolves to a decimal number that identifies the architecture and depends on the -mmcu=mcu option. Possible values are:

2, 25, 3, 31, 35, 4, 5, 51, 6, 102, 104, 105, 106, 107

for mcu=avr2, avr25, avr3, avr31, avr35, avr4, avr5, avr51, avr6, avrxmega2, avrxmega4, avrxmega5, avrxmega6, avrxmega7, respectively. If mcu specifies a device, this built-in macro is set accordingly. For example, with -mmcu=atmega8 the macro will be defined to 4.

Setting -mmcu=device defines this built-in macro which reflects the device's name. For example, -mmcu=atmega8 defines the built-in macro __AVR_ATmega8__, -mmcu=attiny261a defines __AVR_ATtiny261A__, etc.

The built-in macros' names follow the scheme __AVR_Device__ where Device is the device name as from the AVR user manual. The difference between Device in the built-in macro and device in -mmcu=device is that the latter is always lowercase.

If device is not a device but only a core architecture like avr51, this macro will not be defined.

The device / architecture belongs to the XMEGA family of devices.
The device has the the ELPM instruction.
The device has the ELPM Rn,Z and ELPM Rn,Z+ instructions.
The device has the MOVW instruction to perform 16-bit register-register moves.
The device has the LPM Rn,Z and LPM Rn,Z+ instructions.
The device has a hardware multiplier.
The device has the JMP and CALL instructions. This is the case for devices with at least 16 KiB of program memory.
The device has the EIJMP and EICALL instructions. This is the case for devices with more than 128 KiB of program memory. This also means that the program counter (PC) is 3 bytes wide.
The program counter (PC) is 2 bytes wide. This is the case for devices with up to 128 KiB of program memory.
The stack pointer (SP) register is treated as 8-bit respectively 16-bit register by the compiler. The definition of these macros is affected by -mtiny-stack.
The device has the SPH (high part of stack pointer) special function register or has an 8-bit stack pointer, respectively. The definition of these macros is affected by -mmcu= and in the cases of -mmcu=avr2 and -mmcu=avr25 also by -msp8.
The device has the RAMPD, RAMPX, RAMPY, RAMPZ special function register, respectively.
This macro reflects the -mno-interrupts command line option.
Some AVR devices (AT90S8515, ATmega103) must not skip 32-bit instructions because of a hardware erratum. Skip instructions are SBRS, SBRC, SBIS, SBIC and CPSE. The second macro is only defined if __AVR_HAVE_JMP_CALL__ is also set.
The device has Read-Modify-Write instructions (XCH, LAC, LAS and LAT).
Instructions that can address I/O special function registers directly like IN, OUT, SBI, etc. may use a different address as if addressed by an instruction to access RAM like LD or STS. This offset depends on the device architecture and has to be subtracted from the RAM address in order to get the respective I/O address.
The compiler is configured to be used together with AVR-Libc. See the --with-avrlibc configure option.

© Free Software Foundation
Licensed under the GNU Free Documentation License, Version 1.3.